#ChipScope Core Inserter Project File Version 3.0
#Sat Mar 14 15:59:00 CST 2015
Project.device.designInputFile=D\:\\GitHub\\VHDL_Modules\\EEPROM\\MC_25LC640A\\MC_25LC640A_Test_cs.ngc
Project.device.designOutputFile=D\:\\GitHub\\VHDL_Modules\\EEPROM\\MC_25LC640A\\MC_25LC640A_Test_cs.ngc
Project.device.deviceFamily=13
Project.device.enableRPMs=true
Project.device.outputDirectory=D\:\\GitHub\\VHDL_Modules\\EEPROM\\MC_25LC640A\\_ngo
Project.device.useSRL16=true
Project.filter.dimension=10
Project.filter<0>=
Project.filter<1>=*trigg*
Project.filter<2>=BUFG
Project.filter<3>=BUF
Project.filter<4>=BUFGP
Project.filter<5>=RX
Project.filter<6>=SO
Project.filter<7>=OBUF
Project.filter<8>=PORT
Project.filter<9>=SI_IBUF
Project.icon.boundaryScanChain=1
Project.icon.enableExtTriggerIn=false
Project.icon.enableExtTriggerOut=false
Project.icon.triggerInPinName=
Project.icon.triggerOutPinName=
Project.unit.dimension=1
Project.unit<0>.clockChannel=CLK_BUFGP
Project.unit<0>.clockEdge=Rising
Project.unit<0>.dataChannel<0>=LED_OBUF
Project.unit<0>.dataChannel<1>=UART_MODULE/uart_tx_unit/tx_reg
Project.unit<0>.dataChannel<2>=RX_IBUF
Project.unit<0>.dataChannel<3>=EEPROM_MODULE/SPI_INST/Inst_SCLK_CE_GEN/sclk_current
Project.unit<0>.dataChannel<4>=EEPROM_MODULE/SPI_INST/Inst_SCLK_CE_GEN/ce_current
Project.unit<0>.dataChannel<5>=SO_IBUF
Project.unit<0>.dataChannel<6>=EEPROM_MODULE/SPI_INST/Inst_SPI_MASTER_TX/data_reg<7>
Project.unit<0>.dataDepth=16384
Project.unit<0>.dataEqualsTrigger=true
Project.unit<0>.dataPortWidth=7
Project.unit<0>.enableGaps=false
Project.unit<0>.enableStorageQualification=true
Project.unit<0>.enableTimestamps=false
Project.unit<0>.timestampDepth=0
Project.unit<0>.timestampWidth=0
Project.unit<0>.triggerChannel<0><0>=LED_OBUF
Project.unit<0>.triggerChannel<1><0>=UART_MODULE/uart_tx_unit/tx_reg
Project.unit<0>.triggerChannel<1><1>=RX_IBUF
Project.unit<0>.triggerChannel<2><0>=EEPROM_MODULE/SPI_INST/Inst_SCLK_CE_GEN/sclk_current
Project.unit<0>.triggerChannel<2><1>=EEPROM_MODULE/SPI_INST/Inst_SCLK_CE_GEN/ce_current
Project.unit<0>.triggerChannel<2><2>=SO_IBUF
Project.unit<0>.triggerChannel<2><3>=EEPROM_MODULE/SPI_INST/Inst_SPI_MASTER_TX/data_reg<7>
Project.unit<0>.triggerConditionCountWidth=0
Project.unit<0>.triggerMatchCount<0>=1
Project.unit<0>.triggerMatchCount<1>=1
Project.unit<0>.triggerMatchCount<2>=1
Project.unit<0>.triggerMatchCountWidth<0><0>=0
Project.unit<0>.triggerMatchCountWidth<1><0>=0
Project.unit<0>.triggerMatchCountWidth<2><0>=0
Project.unit<0>.triggerMatchType<0><0>=1
Project.unit<0>.triggerMatchType<1><0>=1
Project.unit<0>.triggerMatchType<2><0>=1
Project.unit<0>.triggerPortCount=3
Project.unit<0>.triggerPortIsData<0>=true
Project.unit<0>.triggerPortIsData<1>=true
Project.unit<0>.triggerPortIsData<2>=true
Project.unit<0>.triggerPortWidth<0>=1
Project.unit<0>.triggerPortWidth<1>=2
Project.unit<0>.triggerPortWidth<2>=4
Project.unit<0>.triggerSequencerLevels=16
Project.unit<0>.triggerSequencerType=1
Project.unit<0>.type=ilapro
